Talking about mainstream notebook memory

Modern PCs (including NBs) are multi-bus architectures with memory as the core. That is, the CPU only exchanges information with the main memory through the storage bus (first find the data in the cache, if not, go to the main memory). The input and output devices exchange information directly with the main memory via the I/O bus. Configure a dedicated I/O processor between the I/O device and main memory. The CPU does not directly participate in the transfer of information between the I/O device and the main memory.
Memory is divided into internal memory and external memory (or main memory and auxiliary memory). The internal memory is referred to as memory, which can also be referred to as main memory. In a broad sense, as long as it is a volatile memory inside a PC, it can be regarded as memory, such as video memory, secondary cache, and so on. External memory, also called external memory, is mainly composed of non-volatile memory such as hard disk, optical disk, U disk, memory card, and so on.
Memory as a temporary storage of data, plays a role in connection with, on the one hand to read the executable program and the required data from the external memory, on the other hand also for the CPU services, read and write *. Therefore, the speed of the main memory directly affects the speed of the PC. I will start with the principle of memory.
First, the principle of memory working principle 1. Memory Addressing First of all, the memory from the CPU to find a certain data instruction, and then find out where to access the data (this action is called "addressing"), it first set the abscissa (that is, "column address" ) Then set the ordinate (that is, the "line address"). This is like setting a cross mark on the map. This place is determined very accurately. For computer systems, to find out this place must also determine whether the location is correct, so the computer must also read the signal of the address, the abscissa has a horizontal axis signal (that is, RAS signal, Row Address Strobe) ordinate has ordinate The signal (also known as the CAS signal, Column Address Strobe) is finally read or written. Therefore, there must be at least five steps in the memory for reading and writing: draw a cross (with two addresses for the address and two for the address, and a total of four operations) and or read or write. Can complete memory access *.
2. Memory transfer In order to store data, or read data from the internal memory, the CPU will address the read or write data (that is, we call the cross addressing mode), this time, the CPU will pass the address bus (Address Bus) sends the address to memory, and then the data bus sends the correct data to the microprocessor and sends it back to the CPU.
3. Access time The so-called access time refers to the process time during which the CPU reads or writes data in memory. It is also called the bus cycle. Take reading as an example. When the CPU issues an instruction to the memory, it will request internal access to specific data at a specific address. After the memory responds to the CPU, it sends the data required by the CPU to the CPU until the CPU receives the data. It becomes a reading process. Therefore, the whole process is simply the process of the CPU giving read instructions, memory reply instructions, and throwing data out to the CPU. We often say that 6ns (nanoseconds, seconds -9) refers to the time spent in the above process, and ns is the time unit of the computing operation. We usually use the reciprocal of the access time to express the speed. For example, the actual frequency of the 6ns memory is 1/6ns=166MHz (if it is DDR, it is DDR333, and DDR2 is DDR2 667).
4. Memory Latency The latency of memory (so-called latency, from FSB to DRAM) is a combination of the following: the latency between the FSB and the motherboard chipset (±1 clock cycle), and the delay between the chipset and the DRAM. Time (±1 clock cycle), RAS to CAS latency: RAS (2-3 clock cycles to determine the correct row address), CAS latency (2-3 clock cycles, used to determine the correct column address ), In addition, it takes 1 clock cycle to transfer data, and the data is buffered from the DRAM output through the delay time of the chipset to the CPU (±2 clock cycles).
The general description of the memory delay involves four parameters CAS (Column Address Strobe line address controller) delay, RAS (Row Address Strobe column address controller)-to-CAS delay, RAS Precharge (RAS precharge voltage) delay, Act-to -Precharge (data read time relative to the clock edge) delay. Among them, CAS latency is more important. It reflects the delay in memory from receiving instructions to completing the transmission results. In the data 3-3-3-6 usually seen by everyone, the first parameter is the CAS delay (CL=3). Of course, the smaller the delay, the faster.
Second, the appearance of the article due to the notebook's space design requirements, notebook memory than the desktop memory is narrow, usually using SO-DIMM module specifications, wiring is also more compact, the pin is also the standard 200Pin. The memory we often see, the general components are memory particles, circuit boards, SPD chips, exclusion (terminating resistors) and pins. Let me introduce them separately.
1. Particle memory particles are the integrated circuit blocks that you usually see on the memory. Particles are the main component of memory. The performance of particles can be largely determined by the memory performance. Common particles have the following parameters.
A. Manufacturers of memory chips on the market are Hynix (Hyundai Electronics), Samsung Electronics (Microelectronics), Micro (Micron), Infineon (Infineon), Kingmax (Wintron), and others. However, one thing to note is that "memory particles" and "memory sticks" are completely different things. There are not many companies in the world that can produce memory particles. With the memory particles, the production of memory chips is much simpler, and the producers naturally have much more. There is a fundamental difference between the no-nonsense memory that floods the market and the brand memory, and there are many different costs. Kingston, Kingmax, Golden State and other major brands of memory are used in line with Intel's 6-layer PCB board and memory chips of modern, Samsung and other memory companies, in accordance with strict process production; and those no-name memory although known "Samsung" and "modern" are actually small factories and workshops. They used the cutting angle of memory chips of large companies, soldered them to inferior PCB boards and left the line. The quality is not guaranteed at all, and it is often with some big ones. The distributors form alliances to produce and sell, and price fluctuations are also more susceptible to channel factors.
B. Memory Chip Type Memory Chip Type SDRAM, DDR SDRAM, DDRIISDRAM
SDRAM, DDR SDRAM, and DDR SDRAM are all the same and belong to the SDRAM family. Therefore, the three particles are not easily distinguishable in appearance. However, due to different physical technologies, the three are very different in terms of circuit, delay, and bandwidth. The distinction between the three is usually based on the parameters of the particles or the location of pins and gaps. I will focus on DDR and DDRII technologies later.
C. Memory technology and operating voltage SDRAM memory technology is mainly based on CMOS. The working voltage of the memory is closely related to the chip type of memory. In the specification of JEDEC (Joint Electron Device Engineering Council), the working voltage of SDRAM is It is 3.3V, DDR is 2.5V, and DDRII is 1.8V.
D. Chip Density, Bit Width, and Refresh Rate The chip density is generally expressed in bits (1B=8bit). For example, 16Mbit is 16Mbit and 8bit=2MB. That is, a single chip is 2MB. Another parameter is the bit width. The bit width of the SDRAM system is 64 bits, and the number of particles (usually an even number) used to form 64 bits is also different. For example, a chip is 4bit, then use 16 same chips to form 64bits, if the chip is 16bit then only 4 can be.
For example, 256MB of memory can be composed of 512bits, 8×4, 256MB, and 4×16bit=64bit, which is generally expressed as 512Mbits×16bit or 64MB×16bit. At the refresh rate, the memory bank is composed of electronic memory cells. The refresh process charges the memory cells arranged in a row on the chip. The refresh rate refers to the number of columns that are refreshed. The two commonly used refresh rates are 2K and 4K. The 2K mode can refresh more storage units in a certain period of time and use a shorter time, so the power used by 2K is greater than 4K. The 4K mode uses less time to refresh fewer memory locations, but it uses less power. Some specially designed SDRAMs have an auto-refresh feature that automatically refreshes without CPU or external refresh circuitry. The automatic refresh built inside the DRAM reduces power consumption and is commonly used in notebook computers.
E. Bank
Banks for memory are generally divided into physical Banks and Logical Banks.
The physical bank is embodied in the SDRAM memory module, and the "Bank number" represents the number of physical memory banks of the memory. (Equivalent to "row"/Row).
The logical bank represents the number of logical memory banks within an SDRAM device. (Now is usually 4 banks). In addition, for the main board, it also indicates the DIMM connection slot or slot group, such as Bank 0 or Bank A. The Bank here is the unit of calculation for the memory slot, which is the basic unit of work of the data bus between the computer system and the memory. Only with a BANK, the computer can boot normally. For example, a SDRAM slot has a 64-bit bank, but the old EDO memory was 32-bit, and two memories must be installed to work properly. The bank number on the main board starts from Bank 0 and must be inserted Bank 0 to boot. The slot behind Bank 1 is reserved for future upgrades of the expansion memory.
F. Electrical Interface Type The general electrical interface type corresponds to the memory type. For example, SDRAM is SSTL_3 (3.3V), DDR is SSTL_2 (2.5V), and DDRII is SSTL_18 (1.8V).
G. Memory Packaging Nowadays, there are two types of BGA and TSOP packages. BGA packages are divided into FBGA, μBGA, TinyBGA (KingMAX), and so on. TSOP is divided into TSOPI and TSOPII. BGA package has the characteristics of small chip area, can reduce the area of ​​the PCB board, heat is relatively small, but the need for special welding equipment, can not be hand-welded. In addition, the general BGA packaged chip requires multiple PCB layouts, which imposes requirements on the cost. In addition, the BGA package also has many advantages such as easy chip mounting, better electrical performance, low signal transmission delay, allowing high-frequency operation, superior heat dissipation, etc. It is also reasonable to be the official choice for DDRII. The TSOP technology is relatively mature, low cost, the disadvantage is that the frequency increase is more difficult, larger, and heat larger than the BGA.
H. Speed ​​and delay The speed of general memory is expressed in terms of frequency. For example, we often see SDRAM 133, DDR 266, DDRII533 in fact the physical operating frequency is 133MHz, but uses a different technology, theoretically equivalent to 2 times or 4 times the rate of operation, there is a way to express the pulse is used Cycle to express speed, usually nanoseconds. For example, 1/133 MHz = 7 ns, indicating that the memory pulse cycle is 7 ns. The memory delay I mentioned earlier, the parameter is generally 4 and also useful 3, the smaller the number is, the smaller the delay is, the faster the speed is.
I. Operating temperature Operating temperature: Industrial normal temperature (-40-85 degrees); Extended temperature (-25-85 degrees)
2. Circuit board A circuit board, also known as a PCB board, is the basis of a printed circuit board electronic board, consisting of several layers of conductors and insulators. The lines on the circuit drawings are etched on them and then the electronic components are soldered. Since all the memory components are soldered to the circuit board, the wiring of the circuit board is an important factor in determining the memory stability. According to Intel's specifications, the DDR memory must use a 6-layer PCB board to ensure the memory's electrification function and stable operation. Sex. Therefore, it is recommended that you buy products from big manufacturers, and do not use unsolicited cottage products.
3. SPD and SPD chip SPD (Serial Presence Detect) - serial presence detection, SPD is an 8-pin EEPROM (Electrically Erasable Programmable ROM electronic erasable program read-only memory), capacity is 256 bytes ~ 2KB, inside Mainly saved the relevant data of this memory, such as capacity, chip manufacturer, memory module manufacturer, working speed, whether have ECC check,etc.. The content of the SPD is generally written by a memory module manufacturer. Motherboards that support SPD automatically detect the data in the SPD at startup and set the memory operating parameters accordingly. When the computer is turned on, the BIOS of the PC will automatically read the information recorded in the SPD. If there is no SPD, it is prone to crash or fatal errors. It is recommended that you buy the memory with the SPD chip.
4. Exclusion resistors, also called termination resistors (terminators), are more important hardware in DDR memory. DDR memory imposes high requirements on the working environment. If a previously transmitted signal cannot be completely absorbed by a circuit terminal and a reflection phenomenon is formed on the circuit, it will affect the subsequent signal and cause an operation error. Therefore, DDR motherboards are currently supported by using termination resistors to solve this problem. Since at least one termination resistor is required for each data line, this means that each DDR motherboard requires a large number of termination resistors. This inevitably increases the production cost of the motherboard, and the requirement for termination resistors cannot be completely due to different memory modules. As such, it also caused so-called "memory compatibility problems." Due to the integration of the terminator inside DDR II, this problem has been solved more perfectly.
5. Pin
Pin-pin, the metal contact point on the memory finger. Because different memory pins are different, pins are also the main method of distinguishing various types of memory from the appearance. The memory pins are divided into two sides, for example, the notebook DDR memory is 200Pin, then the front and back pins are 200÷2=100. In addition, some large gold finger manufacturers use advanced technology of electroplating gold production process, pure gold plating layer, effectively improve the oxidation resistance. Ensure the stability of the memory work.
Third, technical articles 1. DDR, DDRII Technology DDR Technology DDR SDRAM is an acronym for Double Data Rate SDRAM. As can be seen from the name, this type of memory is technically inextricably linked with SDRAM.
In fact, DDR memory is an enhanced version of SDRAM memory. DDR uses a more advanced synchronizing circuit, which allows the main steps of the specified address, data transmission and output to be performed independently while maintaining full synchronization with the CPU; DDR uses a DLL (Delay Locked Loop, which provides a data filtering signal) Technology, when the data is valid, the memory controller can use this data filtering signal to accurately locate the data, output it every 16 times, and resynchronize the data from different memory modules. DDL essentially does not need to increase the clock frequency to double the speed of the SDRAM. It allows data to be read on the rising and falling edges of the clock pulse. Theoretically, using the original operating frequency can produce twice the bandwidth.
The same rate of DDR memory and SDR memory, the performance to be more than doubled, can be simply understood as 133MHZ DDR = 266MHZ SDR.
The difference in size between DDR and SDRAM is not large, they have the same size and the same pin distance.
The DDR memory uses the SSTL2 standard that supports 2.5V, instead of the LVTTL standard that uses 3.3V for SDRAM.
However, DDR has its own limitations. DDR is only a simple improvement on the basis of SDRAM. The inherently disturbing characteristics of parallel technology have not been improved, especially with the increase of operating frequency and data transmission speed. The signal interference will cause catastrophic consequences of system instability; in turn, signal interference will also restrict the increase in memory frequency - when the DDR400 specification is developed, the chip core operating frequency reaches 200MHz, and this figure is already very close to the DDR speed. At the limit, only those particles with excellent quality can work stably above 200MHz, so the DDRII standard has become a solution to further increase the memory speed.
DDRII technology DDRII has three major technological innovations compared to DDR, 4-bit prefetch (DDR is 2-bit), Posted CAS, integrated finalizer (ODT), and FBGA/CSP packages.
To explain the concept of prefetching, we must start with the frequency of memory. The "memory frequency" that people usually say is actually a general statement. The memory frequency should actually be subdivided into data frequency, clock frequency, and DRAM core frequency.
The data frequency refers to the frequency of data exchange between the memory module and the system; the clock frequency refers to the frequency of the memory and system coordination; and the DRAM core frequency refers to the operating frequency of the DRAM internal components, and it is only related to the memory itself. Affected by any external factors.
For SDRAM, the three are exactly the same digitally, that is, data frequency = clock frequency = core frequency;
This is not the case with DDR technology, which transmits data twice in one clock cycle. The data frequency is equal to twice the clock frequency, but the core frequency is still equal to the clock frequency. Since the data transmission frequency is doubled (the amount of data transmitted is also doubled), the frequency of the internal core does not change, which means that the DDR chip core must provide twice the amount of data in one cycle to achieve this task. This is the so-called two bit prefetch (2bit Prefect) technology; the 4 bit prefetch used by DDRII. The principle of this technique is to increase the bit width of the DRAM memory matrix by one (two) times so that two (four) times more data can be transmitted in one clock cycle, and these data are then converted to a width of 1/2 (1). The two data streams of /4) are transmitted from the rising and falling edges of each clock cycle.
Posted CAS:DDRII solves the problem of low bandwidth utilization by introducing the “Posted CAS” function. The so-called Posted CAS refers to a clock cycle that inserts the CAS (read/write command) several cycles in advance and directly after the RAS signal. , so that the CAS command can remain valid for the next few cycles, but the read/write operation is not advanced and the total delay time has not changed. The advantage of this approach is that it can completely avoid signal conflicts and improve memory usage efficiency, but it is only reflected in environments where literacy is extremely frequent. If it is a common application, posted CAS functions will increase read latency and degrade system performance. We can turn on or off the posted CAS function through the BIOS as needed (the DDRII in the off state works exactly the same as DDR). The chip integrates the finalizer to improve the stability of the memory operation and enhance the memory compatibility. FBGA package and CSP package, although the package can not directly determine the memory performance, but it is essential to the stable operation of the memory. The FBGA package is the official choice for DDRII, and the FBGA is a BGA system (Ball Grid Array, Ball Grid Array Package), as already mentioned. The biggest feature of the CSP package is that the package area is very close to the chip area, and the ratio is only 1.14:1. It is also the closest chip package technology to the 1:1 ideal situation. In this way, a larger number of memory chips can be accommodated in the same module, which helps to increase the total capacity of the module.
2. Dual-channel memory controller technology The so-called dual-channel DDR, in simple terms, is that the chipset can address and read data on two different data channels. The two memory channels working independently from each other are attached to two independent memory controllers working in parallel with a 64-bit memory bit width, so that the ordinary DDR memory can reach a 128-bit bit width, if it is DDR333. , Dual-channel technology can make it achieve the effect of DDR667, memory bandwidth doubled. Dual-channel DDR has two 64-bit memory controllers. The bandwidth provided by the dual 64-bit memory architecture is equivalent to the bandwidth provided by a 128-bit memory architecture, but the two achieve different results. The dual-channel architecture consists of two separate, complementary, intelligent memory controllers that can operate simultaneously with zero latency between each other. For example, when controller B is ready for the next memory access, controller A is reading/writing main memory and vice versa. This complementary "nature" of the two memory controllers can reduce the effective waiting time by 50%. The dual-channel technology doubles the memory bandwidth. The two memory controllers of the dual-channel DDR are identical in function, and the timing parameters of both controllers can be individually programmed. This flexibility allows users to use three DIMMs with different configurations, capacities, and speeds. Dual-channel DDRs are simply adjusted to the lowest density to achieve 128-bit bandwidth, allowing DIMMs with different densities and latency characteristics to be reliable. To work together. The performance gains from dual-channel DDR technology are evident, with DDR266 providing 2.1GB/s of bandwidth while dual-channel DDR266 provides 4.2GB/s of bandwidth. By analogy, dual channel DDR333 and DDR400 can reach 5.4GB/s and 6.4GB/s.
3. CPU Integrated Memory Controller Technology This is AMD's technology for improving CPU and memory performance. This technology is a technology that integrates the Northbridge memory controller into the CPU. The use of this technology makes the CPU- The Northbridge-memory three-way data transmission process is directly simplified to a single transmission technology between the CPU and the memory, and its latency latency is reduced, improving the memory work efficiency. The purpose of doing this is to liberate the Northbridge of the system. As we all know, the graphics card also transfers data to the CPU through the Northbridge. Although the GeForce256 era has a GPU, but with the progress of the game, the screen is gorgeous, not Less data still requires the CPU to do ancillary processing. The transmission of these data to the CPU must go through the north bridge of the system. Because the AMD64 system integrates the memory control into the master, the Northbridge with reduced pressure can better serve the graphics card. In addition, the lack of intermediate links, data exchange between memory and CPU appears more smooth. However, this technology also has its drawbacks. When new memory technologies emerge, they must be replaced by CPUs. This adds intangible costs.
4. Other technologies A. ECC memory full name Error Checkingand Correcting. It is also implemented by adding bits to the original data bits. For 8-bit data, 1 bit is used for Parity test and 5 bits are used for ECC. This extra 5 bits is used to reconstruct the wrong data. When the number of bits of data doubles, Parity also doubles, while ECC only needs to increase one bit. When the data is 64 bits, the same ECC and Parity bits are used (both are. Only errors can be detected in those Parity. Locally, ECC can correct most errors.If you work normally, you will not find out that your data is wrong, only after memory error correction, the computer's instructions can continue to be executed.Of course, when the error correction system Performance has been significantly reduced, but this error correction is very important for applications such as servers. ECC memory is much more expensive than normal memory.
B. (Un) Buffered Memory (Un)Buffered Memory, (not) memory with cache. The cache can push the signal through the memory chip twice, and more memory chips can be placed on the memory bar. Memory with cache and memory without cache cannot be mixed. The memory controller structure of the computer determines whether the computer has cached memory or no cached memory.
IV. Summary articles Q&A
With the development of the entire PC industry, the development of memory is moving faster, with lower power consumption and lower cost. The old generation of DDR memory is facing more new technology challenges, whether it is the same DDRII or Rambus. XDR and VIA's QBM are all competitive.
As an ordinary book user, we are more concerned with mature technology, product cost-effective products, because the memory expansion of the books relative to other hardware is easier, it is recommended that everyone in the capital allows the best to increase the memory capacity. In particular, integrated graphics books, but also consider upgrading to dual-channel, to improve the overall performance of graphics cards and systems.
1. What are the conditions for forming a dual channel?
First of all, the formation of dual-channel memory requires the motherboard or CPU integrated dual-channel memory controller to be able to, and second, need two memory slots, I have said before, a DDR SDRAM slot is 64bit, to form a 128bit dual channel must Two memory slots are available. Thirdly, what needs to be emphasized is the requirement for memory modules. Intel official documents have strict restrictions on the formation of dual-channel memory modules. They must be the same capacity and the same structure (such as the number of single-sided, double-sided, or memory particles, each The parameters such as the bit width of the particles must be the same) and the memory of the same brand (the SPD information of different brands of memory may be different). Of course, this is just the requirement that Intel put forward to ensure the normal operation of dual channels. Everything is absolute, there will be some other combinations, if you have experience in this area, you can reply exchanges.
2. How to upgrade notebook memory.
The upgrade of the memory of the notebook can, in principle, be “Hanshin’s point-to-point soldier, and the more the better”. But there are several aspects to consider.
Type: Due to the different definition of DDR and DDRII pins, the operating voltage is also different, so they cannot be intermixed, otherwise they will burn out the memory or memory slot.
Capacity: try to select a single large capacity, if not a dual channel, try to choose a single 512MB or more.
Speed: First of all to consider the chipset's specifications, try to meet the maximum requirements of the chipset to buy, and second, to ensure the same frequency of two memories, if the original memory is DDR266, buy a DDR333 memory can only run on the frequency of DDR266 Can not play true performance.
Structure: In theory, whether it is expansion, stability or compatibility, single-sided structure is better than double-sided structure. Considering the amount of heat, single-sided memory is smaller than double-sided memory. The single and double-sided memory itself is not good or bad, and the difference is also very small. The memory of the same capacity has a higher degree of integration of one side than two sides, and the production date depends on the latter, so the work becomes more stable.
3. How to identify memory particles.
Since there is no relatively uniform standard, the particles of various manufacturers are not the same. I give some common Baidu search results of particle manufacturers, we can view according to their own needs.
Hynix (modern electronics)
Samsung Electronics (Samsung Electronics)
Micro (Micron)
Infineon (Infineon)
Kingmax
GEIL
Mosel (Mao, Taiwan)
Nanya (South Asia)
Apacer (Apacer)
V(A)-data (Avatar Technology)
TOSHIBA (Toshiba)

Wooden Display

Cardboard Floor Display,Cardboard Counter Display Co., Ltd. , http://www.chcosmeticdisplay.com

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