Describes how to compile the Xilinx libraries and structure simulations necessary for HDL. Creating a directory where the library will be compiled Before compiling the library, it is best to create a directory (in fact, you must create a directory), as follows. (Assuming Modelsim's installation directory is "$Modeltech_6.0", ISE's installation directory is "$Xilinx") ◆ Create a folder named XilinxLib in the "$Modeltech_6.0/" directory; ◆ After starting Modelsim, from Click on "Change Directory" in the "File" menu item and assign it to the folder "XilinxLib" that was just created; ◆ The next thing to do is to compile the Xilinx library into the "XilinxLib" folder. There are three libraries that need to be compiled. They are "simprims", "unisims" and "XilinxCoreLib"; (all of these libraries are in the "$Xilinx/verilog/src" directory) ◆ Click on the "Workspace" window in Modelsim to create a new one called Xilinx_CoreLib Library; (This operation creates a folder called "Xilinx_CoreLib", you can see it in the "Workspace" window) ◆ Start compiling now! Click "Compile" in the "Compile" menu, select all the files in the "$Xinlinx/verilog/scr/XilinxCoreLib" directory, select the "Xilinx_CoreLib" folder you just created in the pop-up dialog box, and click the "Compile" button. You can compile it; ◆ Compile the other two local libraries ("simprims" and "unisims") in the same way; Chapter 2 calls Xilinx CORE-Generator when you need to generate parameterized and free IP cores in the design (black CORE-Generator is a very useful program when it comes to the schematic or HDL. Creating an IP Core with CORE-Generator It is very simple to use the CORE-Generator provided by Xilinx to generate an IP core. The kernel is fully parameterized, which means you only need to fill in a few numbers and parameters in the space, and the program will automatically generate the kernel you need. (Some kernels are all free and some are not so generous.) The steps to generate an IP core using CORE-Generator are as follows: ◆ Find the "Xilinx" item in "Programs" and then start the separate "CORE" in "Accessories" -Generator"; ◆ Select the appropriate FPGA model in the "Part" tab; ◆ Select the correct design stream from the "GeneraTIon" tab bar; (press "OK" button when finished) ◆ Customize your parameterized kernel; At the same time as the kernel is generated, a “Readme File†message box will pop up to inform some important information. ◆ “*.v†files are used for simulation and synthesis, while “*.veo†files are used. Used as a comprehensive example. (Calling means adding the corresponding file to the Synplify.Pro project, and the instance means that some lines in the file can be copied to the top-level module of the HDL design. Exit!) Chapter 3 Using Synplify.Pro to Integrate HDL And kernel synthesis is the technique of transforming designed HDL code, graphics code and schematic into logical units. Compared to physical synthesis that is very close to hardware execution and physical routing, logic synthesis is a higher level of synthesis. Synthesizing with Synplify.Pro Synplify.Pro has a very good comprehensive capability for the high-volume, low-priced Xilinx Spartan family of FPGAs. The specific steps are as follows: ◆ First create a project; ◆ Add HDL files to the project (My demo file has three files, CORE-Generator generates "async_fifo.v" and "dcm4clk" and a Verilog top-level file "top.v" ). Set "ImplementaTIon OpTIon" in the Synplify.Pro environment; (If you are very skilled, you can omit this step) ◆ Insert the two Verilog files generated by CORE-Generator into the instructions that Synplify.Pro can recognize. These instructions tell the synthesizer how to Handle these two special files; ◆ Insert "/*synthesis syn_black_box*/" to instruct Synplify.Pro to treat the module as a black box, and indicate "/*synthesis syn_isclock=1*/" to indicate this as the clock input The port cannot be recognized by the synthesizer because it has no underlying structure except the port name; ◆ Save the project in the appropriate place and then synthesize the project; ◆ After the integration is complete, select the “Technology View†button to observe the hierarchy; You can find the kernel ◆ Believe it or not! Synplify.Pro has generated what you want. (There is a dedicated Clock-Input-Buffer, IBUG-connected DCM structure, and a feedback from Global-Clock-Buffer, BUFG Structure "CLKFB") Chapter 4 After the integration of the project execution is to download the generated bit file to The final step of the FPGA. Simultaneously create different timing models (post-translate model, post-map model and post-PAR model) and timing reports. ISE, the only tool ISE that can be used to execute controls all aspects of the design flow. Through the Project Navigator interface, you can access all the different design entities and actual execution tools. You can also access project-related files and documents. The Project Navigator contains a flat directory structure; in the demonstration project, some of ISE's poor features are not allowed. Don't give way to other third-party software, such as ModelSim.Pro and Synplify.Pro, so ISE is generally only used as an execution tool. ◆ Start ISE, use "EDIF" as the file input; ("EDIF" file by Synplify.Pro Software generation, as a terminal design file, can be recognized by most FPGA development environments, such as ISE, Quartus, ispLevel.) ◆ After the ISE project is built, you can add two other files, one is related to the kernel. Xco" file, the other is "*.xaw" related to the DCM structure; Really all modules; (click on the red line option) ◆ If you want to emulate the post-PAR module, it is best to first define the pin, especially the dedicated external clock pin; ◆ Start the "Floorplaner" in the "map" program Options to define pins; ◆ “DCMs†and “IBUFGs†should be placed in the correct position. Simulation is one of the debugging methods used to verify that the timing and functionality of the design is correct. Four different types of simulations should be performed during the verification of the debug circuit and the observation of the waveform. Different simulation types are targeted at different platforms. Functional simulation is used to verify that the design is functioning correctly; post-translate simulation is used to verify the design-based primitive delay; post-map simulation is used to simulate primitive-based delays and network delays; finally, post-PAR simulation is The post-map simulation adds input and output and routing delays. I won't give a full detailed simulation of the demo design, but give the key steps and important steps. Only the post-PAR simulation process is given, listing the different files needed for all three other simulations. (Actually, different files are different reference timing models:
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