This article summarizes a total of 268 design specifications for PCB layout and layout and circuit design. Let's share it with you.
| Classified by location | Technical specification content | |
| 1 | PCB layout and layout | PCB layout and layout isolation criteria: strong and weak current isolation, size and voltage isolation, high and low frequency isolation, input and output isolation, digital analog isolation, input and output isolation, and the demarcation standard is one order of magnitude. The isolation method includes: the space is far away, and the ground line is separated. |
| 2 | PCB layout and layout | The crystal should be as close as possible to the IC, and the wiring should be thicker. |
| 3 | PCB layout and layout | Crystal housing ground |
| 4 | PCB layout and layout | When the clock wiring is output through the connector, the pins on the connector are covered with ground pins around the clock line pins. |
| 5 | PCB layout and layout | Let the analog and digital circuits have their own power and ground paths. Whenever possible, widen the power and ground of these two circuits or use separate power and ground planes to reduce power and ground. The impedance of the line loop reduces any interference voltage that may be in the power and ground loops |
| 6 | PCB layout and layout | The analog ground and digital ground of the PCB working alone can be connected at a single point near the system grounding point. If the power supply voltage is consistent, the power supply of the analog and digital circuits is connected at a single point at the power inlet. If the power supply voltage is inconsistent, the power supply is close. A 1~2nf capacitor provides a path for the signal return current between the two power supplies. |
| 7 | PCB layout and layout | If the PCB is plugged into the motherboard, the power and ground of the analog and digital circuits of the motherboard are also separated. The analog ground and the digital ground are grounded at the ground of the motherboard, and the power supply is connected at a single point near the system ground. If the power supply voltage is the same, the power supply of the analog and digital circuits is connected at a single point of the power inlet. If the power supply voltage is inconsistent, a capacitor of 1~2nf is located near the two power supplies to provide a path for the signal return current between the two power sources. |
| 8 | PCB layout and layout | When high-speed, medium-speed, and low-speed digital circuits are mixed, they are assigned different layout areas on the printed board. |
| 9 | PCB layout and layout | Separate low-level analog circuits and digital logic circuits as much as possible |
| 10 | PCB layout and layout | When designing a multilayer printed board, the power plane should be close to the ground plane and placed below the ground plane. |
| 11 | PCB layout and layout | The wiring layer should be arranged adjacent to the entire metal plane when designing the multilayer printed board |
| 12 | PCB layout and layout | The multi-layer printed board is designed to separate the digital circuit from the analog circuit, and the digital circuit and the analog circuit are arranged in different layers when conditions permit. If it must be arranged in the same layer, it can be remedied by ditching, adding grounding lines, separating and so on. The analog and digital ground and power supplies must be separated and cannot be mixed. |
| 13 | PCB layout and layout | Clock circuits and high-frequency circuits are the main sources of interference and radiation, and must be arranged separately from remote circuits. |
| 14 | PCB layout and layout | Pay attention to waveform distortion during long-distance transmission |
| 15 | PCB layout and layout | To reduce the loop area of ​​the interference source and the sensitive circuit, the best way is to twist the signal line and the ground line (or current-carrying circuit) with twisted pair and shielded wires to make the signal and ground line (or Nearest distance between current carrying loops) |
| 16 | PCB layout and layout | Increase the distance between the lines so that the mutual inductance between the interferer and the sensed line is as small as possible |
| 17 | PCB layout and layout | If possible, the line of the interference source is routed at right angles (or near right angles) to the sensed line, which greatly reduces the coupling between the two lines. |
| 18 | PCB layout and layout | Increasing the distance between lines is the best way to reduce capacitive coupling |
| 19 | PCB layout and layout | Before the formal wiring, the first point is to classify the lines. The main classification method is based on the power level and is divided into groups at every 30 dB power level. |
| 20 | PCB layout and layout | Wires of different classifications should be bundled separately and laid separately. For adjacent types of wires, they can also be put together after taking measures such as shielding or twisting. The minimum distance between the wire harnesses for sorting is 50~75mm |
| twenty one | PCB layout and layout | In the resistor layout, the gain control resistor and bias resistor (up and down) of the amplifier, pull-up and regulation rectifier circuit should be as close as possible to the amplifier, active device and its power supply and ground to reduce its decoupling effect (improve the transient response). time). |
| twenty two | PCB layout and layout | The bypass capacitor is placed close to the power input |
| twenty three | PCB layout and layout | The decoupling capacitor is placed at the power input. As close as possible to each IC |
| twenty four | PCB layout and layout | Basic PCB characteristics Impedance: determined by the quality of the copper and cross-sectional area. Specifically: 1 ounce 0.49 milliohms per unit area |
| Capacitance: C=EoErA/h, Eo: free space dielectric constant, Er: PCB substrate dielectric constant, A: current reaching range, h: trace spacing | ||
| Inductance: average distribution in the wiring, about 1nH / m | ||
| For ounces of copper wire, a 0.5mm wide, 20mm long line above the ground plane can produce 9.8 milliohms of impedance, 20nH of inductance and ground between 0.25mm (10mil) thick FR4 1.66pF coupling capacitor. | ||
| 25 | PCB layout and layout | Basic guidelines for PCB layout: increase the trace spacing to reduce crosstalk of capacitive coupling; parallelly lay power and ground lines to optimize PCB capacitance; place sensitive high frequency lines away from high noise power lines; widen power supply Line and ground to reduce the impedance of the power and ground lines; |
| 26 | PCB layout and layout | Segmentation: Physical segmentation to reduce coupling between different types of signal lines, especially power and ground |
| 27 | PCB layout and layout | Local decoupling: Decoupling the local power supply and the IC, using a large-capacity bypass capacitor between the power input port and the PCB for low-frequency ripple filtering and meeting the burst power requirement, and adopting between the power supply of each IC and the ground. For coupling capacitors, these decoupling capacitors should be as close as possible to the pins. |
| 28 | PCB layout and layout | Wiring separation: Minimize crosstalk and noise coupling between adjacent lines in the same layer of PCB. The 3W specification is used to handle critical signal paths. |
| 29 | PCB layout and layout | Protection and shunt line: use two-side ground protection for key signals, and ensure that both ends of the protection line are grounded |
| 30 | PCB layout and layout | Single-layer PCB: The ground wire should be at least 1.5mm wide, and the jumper and ground line width should be kept to a minimum. |
| 31 | PCB layout and layout | Double-layer PCB: The ground grid/dot matrix wiring is used preferentially, and the width is maintained at 1.5mm or more. Or put the ground aside and put the signal power on the other side |
| 32 | PCB layout and layout | Protection ring: use a ground wire to form a ring, and surround the protection logic for isolation. |
| 33 | PCB layout and layout | PCB Capacitors: PCB capacitors are created on the multilayer board due to the power plane and a thin layer of ground insulation. The advantage is that there is a very high frequency response and a low series inductance that is evenly distributed over the entire surface or the entire line. Equivalent to a decoupling capacitor that is evenly distributed across the board. |
| 34 | PCB layout and layout | High-speed circuits and low-speed circuits: High-speed circuits should be brought close to the ground plane, and low-speed circuits should be close to the power plane. |
| Copper fill of the ground: copper fill must ensure grounding. | ||
| 35 | PCB layout and layout | The routing direction of adjacent layers is orthogonal, avoiding different signal lines in the same direction in adjacent layers to reduce unnecessary interlayer interference; when it is difficult to avoid due to board structure limitations (such as some backplanes) This situation occurs, especially when the signal rate is high, it should be considered to isolate the wiring layers with the ground plane and isolate the signal lines with the ground signal lines; |
| 36 | PCB layout and layout | Wiring with one end floating is not allowed, in order to avoid "antenna effect". |
| 37 | PCB layout and layout | Impedance matching check rule: The wiring width of the same grid should be consistent. The variation of the line width will cause the line characteristic impedance to be uneven. When the transmission speed is high, reflection will occur, which should be avoided in the design. Under certain conditions, variations in line width may not be avoided and the effective length of the inconsistent portion of the middle should be minimized. |
| 38 | PCB layout and layout | Prevent the signal line from forming a self-loop between different layers, and the self-loop will cause radiation interference. |
| 39 | PCB layout and layout | Short-term rules: The wiring should be as short as possible, especially for important signal lines, such as clock lines, and keep the oscillator close to the device. |
| 40 | PCB layout and layout | Chamfer rule: Avoid sharp angles and right angles in PCB design, generate unnecessary radiation, and the process performance is not good. The angle between all lines and lines should be greater than 135 degrees. |
| 41 | PCB layout and layout | The line connecting the filter capacitor pad to the lands should be connected by a thick line of 0.3mm, and the length of the interconnection should be ≤1.27mm. |
| 42 | PCB layout and layout | In general, the high frequency part is placed in the interface part to reduce the wiring length. At the same time, we must also consider the segmentation problem of the ground plane in the high/low frequency part. Usually, the ground of the two is divided, and then the single point is connected at the interface. |
| 43 | PCB layout and layout | For areas with dense vias, care should be taken to avoid interconnecting the power supply and the hollowed out areas of the formation to form a split of the planar layer, thereby destroying the integrity of the planar layer and, in turn, increasing the loop area of ​​the signal line in the formation. |
| 44 | PCB layout and layout | Power layer projection non-overlapping criteria: PCB boards with more than two layers (including), different power layers should avoid overlap in space, mainly to reduce interference between different power supplies, especially between power supplies with large voltage differences. The overlap of the power plane must be avoided. If it is difficult to avoid, consider the middle interval. |
| 45 | PCB layout and layout | 3W rule: In order to reduce the interference between lines, it should be ensured that the line spacing is large enough. When the line center distance is not less than 3 times the line width, 70% of the electric fields can be kept from interfering with each other. If 98% of the electric fields do not interfere with each other, , 10W rules can be used. |
| 46 | PCB layout and layout | 20H criterion: With an H (media thickness between power and ground), if the internal contraction is 20H, 70% of the electric field can be confined to the grounding edge, and if it is 1000H, the 98% electric field can be limited. |
| 47 | PCB layout and layout | Five-five criteria: printed board layer selection rules, that is, the clock frequency to 5MHZ or pulse rise time is less than 5ns, the PCB board must use multi-layer board, such as the use of double-layer board, it is best to use one side of the printed board as a Complete ground plane |
| 48 | PCB layout and layout | Mixed-signal PCB zoning guidelines: 1 partition the PCB into separate analog and digital sections; 2 place the A/D converter across the partition; 3 do not divide the ground, and place it uniformly under the analog and digital sections of the board 4 In all layers of the board, the digital signal can only be wired in the digital part of the board, the analog signal can only be wired in the analog part of the board; 5 to achieve analog power and digital power split; 6 wiring can not cross the split power plane The gap between the 7; the signal line that must cross the gap between the divided power sources should be located on the wiring layer adjacent to the large area; 8 analyze the path and mode through which the return current actually flows; |
| 49 | PCB layout and layout | Multi-layer boards are a good board-level EMC protection design measure and are recommended. |
| 50 | PCB layout and layout | The signal circuit and the power circuit are independent grounding wires, and finally grounded at one point. They should not have a common grounding wire. |
| 51 | PCB layout and layout | The signal return ground wire uses a separate low-impedance ground loop, and no chassis or structural frame can be used as a loop. |
| 52 | PCB layout and layout | When the equipment working in the medium and short wave is connected to the earth, the grounding wire is <1/4λ; if the requirement is not met, the grounding wire cannot be an odd multiple of 1/4λ. |
| 53 | PCB layout and layout | The ground line of the strong signal and the weak signal should be arranged separately and connected to the ground network only one point. |
| 54 | PCB layout and layout | There must be at least three separate ground lines in the general equipment: one is the low-level circuit ground (called the signal ground), and the other is the relay, the motor, and the high-level circuit ground (called the interference ground or noise ground). The other is that when the equipment uses AC power, the safe ground wire of the power supply should be connected to the ground wire of the casing, and the casing and the box are insulated, but the two are the same at one point. Finally, all the ground wires are grounded at one point. . The breaker circuit is grounded at a single point at the maximum current point. When f<1MHz, one point is grounded; when f>10MHz, multi-point is grounded; 1MHz |
| 55 | PCB layout and layout | Avoid ground loop guidelines: Power lines should be routed parallel to ground. |
| 56 | PCB layout and layout | The heatsink should be connected to the power ground or shielding ground or protective ground in the board (preferably connect the shielding ground or the protective ground) to reduce the radiation interference. |
| 57 | PCB layout and layout | Digital ground is separated from analog ground, grounding is widened |
| 58 | PCB layout and layout | Pay attention to different layout areas when mixing high speed, medium speed and low speed |
| 59 | PCB layout and layout | Dedicated zero-volt line, the trace width of the power line is ≥1mm |
| 60 | PCB layout and layout | The power and ground wires are placed as close as possible, and the power and ground on the entire printed board are distributed in a "well" shape to equalize the distribution line current. |
| 61 | PCB layout and layout | As far as possible, the interference source line and the sense line are wired at right angles |
| 62 | PCB layout and layout | According to the power classification, the wires of different classifications should be bundled separately, and the distance between the bundles laid separately should be 50-75mm. |
| 63 | PCB layout and layout | In the case of high requirements, the inner conductor should be provided with a 360° complete package, and the coaxial connector should be used to ensure the integrity of the electric field shielding. |
| 64 | PCB layout and layout | Multilayer board: The power layer and the ground plane are adjacent. The high speed signal should be close to the ground plane and the non-critical signal should be placed close to the power plane. |
| 65 | PCB layout and layout | Power: When the circuit requires multiple power supplies, separate each power supply with ground. |
| 66 | PCB layout and layout | Via: For high speed signals, the via produces an inductance of 1-4nH and a capacitance of 0.3-0.8pF. Therefore, the vias of the high-speed channel should be as small as possible. Make sure that the number of vias on the high-speed parallel lines is the same. |
| 67 | PCB layout and layout | Short cut: Avoid using stubs on high frequency and sensitive signal lines |
| 68 | PCB layout and layout | Star signal arrangement: avoiding high speed and sensitive signal lines |
| 69 | PCB layout and layout | Radiated signal arrangement: Avoid high-speed and sensitive lines, keep the signal path width constant, and do not be too dense through the power supply surface and ground. |
| 70 | PCB layout and layout | Ground loop area: Keeping the signal path and its ground return line close together will help minimize the ground loop |
| 71 | PCB layout and layout | Generally, the clock circuit is placed at the center of the PCB or at a well-grounded position, so that the clock is as close as possible to the microprocessor, and the leads are kept as short as possible, and the quartz crystal is oscillated only to the ground of the case. |
| 72 | PCB layout and layout | In order to further enhance the reliability of the clock circuit, the ground line can be used to find the clock area to isolate, and the grounding area is increased under the crystal oscillator to avoid other signal lines; |
| 73 | PCB layout and layout | The principle of component layout is to divide the analog circuit part and the digital circuit part, divide the high-speed circuit and the low-speed circuit, divide the high-power circuit and the small-signal circuit, divide the noise component and the non-noise component, and minimize the between components. Leads minimize interference with each other. |
| 74 | PCB layout and layout | The circuit board is divided according to functions, and the ground lines of each partition circuit are connected in parallel with each other and grounded at one point. When there are multiple circuit units on the circuit board, each unit should have independent ground return, each unit is connected to the common ground, single-panel and double-panel single-point power supply and single-point grounding. |
| 75 | PCB layout and layout | The important signal lines are as short and thick as possible, and the ground is added to both sides. The signals need to be led out through the flat cable and used in the form of "ground-signal-ground". |
| 76 | PCB layout and layout | I/O interface circuit and power drive circuit as close as possible to the edge of the printed board |
| 77 | PCB layout and layout | In addition to the clock circuit, noise-sensitive devices and circuits are also avoided as much as possible. |
| 78 | PCB layout and layout | When there is a high-speed data interface such as PCI or ISA in the printed circuit board period, it is necessary to pay attention to the progressive layout of the signal frequency on the circuit board, that is, the high-frequency circuit, the medium-frequency circuit and the low-frequency circuit are sequentially arranged from the slot interface portion, so that the generation is easy. The disturbing circuitry is remote from the data interface. |
| 79 | PCB layout and layout | The shorter the lead of the signal on the printed circuit, the longer the length should not exceed 25cm, and the number of vias should be as small as possible. |
| 80 | PCB layout and layout | When the signal line needs to be turned, use 45 degree or circular arc wiring to avoid using 90 degree polyline to reduce the reflection of high frequency signals. |
| 81 | PCB layout and layout | Avoid 90 degree fold lines when wiring, reduce high frequency noise emission |
| 82 | PCB layout and layout | Pay attention to the crystal wiring. The crystal oscillator and the MCU pins are placed as close as possible, and the clock region is isolated by the ground wire. The crystal oscillator case is grounded and fixed. |
| 83 | PCB layout and layout | The board is reasonably partitioned, such as strong and weak signals, digital and analog signals. Keep interference sources (such as motors, relays) and sensitive components (such as microcontrollers) as far as possible |
| 84 | PCB layout and layout | The digital area is isolated from the analog area by a ground line, the digital ground is separated from the analog ground, and finally connected to the power ground at a point. The A/D and D/A chip layouts are also based on this principle. Manufacturers have already considered this requirement when assigning A/D and D/A chip pinouts. |
| 85 | PCB layout and layout | The ground wire of the MCU and high-power devices should be grounded separately to reduce mutual interference. High-power devices are placed on the edge of the board as much as possible |
| 86 | PCB layout and layout | Minimize the loop loop area during wiring to reduce induced noise |
| 87 | PCB layout and layout | When wiring, the power and ground wires should be as thick as possible. In addition to reducing the voltage drop, it is more important to reduce the coupling noise. |
| 88 | PCB layout and layout | IC devices are soldered directly to the board as much as possible, with fewer IC seats |
| 89 | PCB layout and layout | The reference point should generally be placed at the intersection of the left and bottom border lines (or the intersection of the extension lines) or the first pad on the board's insert. |
| 90 | PCB layout and layout | The layout is recommended to use a 25mil grid |
| 91 | PCB layout and layout | The total connection is as short as possible and the key signal line is the shortest |
| 92 | PCB layout and layout | Elements of the same type should be identical in the X or Y direction. The same type of polar discrete components must also strive to be consistent in the X or Y direction for ease of production and commissioning; |
| 93 | PCB layout and layout | The components should be placed for easy commissioning and maintenance. Small components should not be placed on the side of the large components. There should be sufficient space around the components to be debugged. The heating element should have enough space to facilitate heat dissipation. The thermal element should be kept away from the heating element. |
| 94 | PCB layout and layout | The distance between the two in-line components is >2 mm. The distance between the BGA and the adjacent device is >5mm. The small components of the resistive capacitors and the like have a distance of >0.7 mm. The outside of the chip component pad and the outside of the adjacent component pad are >2 mm. No plug-in components can be placed within 5 mm of the crimping element. Mounting components should not be placed within 5 mm of the soldered surface. |
| 95 | PCB layout and layout | The decoupling capacitor of the integrated circuit should be as close as possible to the power supply pin of the chip, and the high frequency is the closest. Make the shortest path between the power supply and the ground. |
| 96 | PCB layout and layout | The bypass capacitor should be evenly distributed around the integrated circuit. |
| 97 | PCB layout and layout | When using components, components using the same power supply should be considered as close together as possible for future power splitting. |
| 98 | PCB layout and layout | The placement of the resistive container for impedance matching purposes should be reasonably laid out according to its properties. |
| 99 | PCB layout and layout | The layout of the matching capacitor resistors should be clearly defined. For multi-load terminal matching, it must be placed at the farthest end of the signal for matching. |
| 100 | PCB layout and layout | The matching resistor layout should be close to the driving end of the signal, and the distance is generally no more than 500 mils. |
| 101 | PCB layout and layout | Adjust the characters, all characters can not be above the disk, to ensure that the character information can be clearly seen after assembly, all characters should be consistent in the X or Y direction. Characters and silk screens must be uniform in size. |
| 102 | PCB layout and layout | Key signal line priority: priority transmission of key signals such as power supply, analog small signal, high speed signal, clock signal and synchronization signal; |
| 103 | PCB layout and layout | The minimum rule of the loop: that is, the ring area composed of the signal line and its loop should be as small as possible, the ring area should be as small as possible, and the smaller the ring area, the less external radiation, and the smaller the interference from the outside. In the double-layer board design, in the case of leaving enough space for the power supply, the remaining part should be filled with reference ground, and some necessary vias should be added to effectively connect the double-sided signals. Grounding isolation is adopted. For some designs with higher frequencies, special consideration should be given to other planar signal loops. It is recommended to use multi-layer boards. |
| 104 | PCB layout and layout | Grounding lead minimum criteria: Minimize and thicken the grounding leads (especially high frequency circuits). For circuits operating at different levels, long common ground lines are not available. |
| 105 | PCB layout and layout | If the internal circuit is to be connected to the metal case, use a single point ground to prevent the discharge current from flowing through the internal circuit. |
| 106 | PCB layout and layout | Components that are sensitive to electromagnetic interference should be shielded from components or lines that can generate electromagnetic interference. If such lines must pass by the part, they should be used at an angle of 90°. |
| 107 | PCB layout and layout | The wiring layer should be arranged adjacent to the entire metal plane. This arrangement is to generate flux cancellation |
| 108 | PCB layout and layout | There are many loops between the grounding points. The diameter of these loops (or grounding point spacing) should be less than 1/20 of the highest frequency wavelength. |
| 109 | PCB layout and layout | The power cable and ground wire of single or double panel should be as close as possible. The best way is to connect the power cable to one side of the printed board, and the ground wire to the other side of the printed board. The impedance is the lowest |
| 110 | PCB layout and layout | Signal traces (especially high frequency signals) should be as short as possible |
| 111 | PCB layout and layout | The distance between the two conductors shall comply with the provisions of the electrical safety design specification. The voltage difference shall not exceed the breakdown voltage of the air and the insulating medium between them, otherwise an arc will be generated. In the 0.7ns to 10ns time, the arc current can reach tens of A, and sometimes even exceed 100 amps. The arc will remain until the two conductors are shorted or the current is low enough to sustain the arc. Examples of possible spikes are hand or metal objects, which are identified during design. |
| 112 | PCB layout and layout | Add a ground plane immediately adjacent the double panel and connect the ground plane to the ground point on the circuit at the shortest spacing. |
| 113 | PCB layout and layout | Make sure that each cable entry point is within 40mm (1.6 inches) of the chassis ground. |
| 114 | PCB layout and layout | Connect the connector housing and the metal switch housing to the chassis ground. |
| 115 | PCB layout and layout | Place a wide conductive guard ring around the membrane keyboard, attach the outer perimeter of the ring to the metal chassis, or connect to the metal chassis at least at the four corners. Do not connect the guard ring to the PCB ground. |
| 116 | PCB layout and layout | Use of multi-layer PCB: Compared to Double-sided PCB, ground plane and power plane and tightly packed signal line-ground spacing can reduce common impedance and inductive coupling to achieve double-sided PCB /10 to 1/100. Try to keep each signal layer close to a power or ground plane. |
| 117 | PCB layout and layout | For high-density PCBs with components on the top and bottom surfaces, short traces, and lots of fill, the inner trace can be used. Most of the signal lines, as well as the power and ground planes, are on the inner layer and are therefore similar to Faraday boxes with shielding. |
| 118 | PCB layout and layout | Place all connectors on the side of the board as much as possible. |
| 119 | PCB layout and layout | Place a wide chassis ground or polygon fill on all PCB layers underneath the connector (which is easily hit directly by the ESD) and connect them with vias every approximately 13 mm. |
| 120 | PCB layout and layout | When assembling the PCB, do not apply any solder to the top or bottom mounting hole pads. Use a screw with an inset washer to make the PCB in close contact with the metal chassis/shield or ground plane bracket. |
| 121 | PCB layout and layout | The same "isolation zone" is set between the chassis ground and circuit ground of each layer; if possible, the separation distance is 0.64 mm (0.025 inch). |
| 122 | PCB layout and layout | A circular ring is placed around the circuit to prevent ESD interference: 1 put a circular path on the entire circumference of the board; 2 the annular width of all layers is >2.5mm (0.1 inch); 3 every 13mm (0.5 inch) with a via hole Connected together; 4 connects the ring ground to the common ground of the multilayer circuit; 5 pairs of double panels installed in the metal chassis or shielding device should be connected to the circuit in common; 6 unshielded The double-sided circuit is connected annularly to the chassis ground, and no solder resist is applied annularly so that the annular discharge can act as a discharge rod for the ESD, at least one 0.5 mm wide at a position on the annular ground (all layers) ( 0.020") gap to avoid large ground loops; 7 If the board is not placed in a metal chassis or shield, solder resists should not be applied to the top and bottom chassis grounds of the board so they can be used as ESD A discharge rod for an electric arc. |
| 123 | PCB layout and layout | In the area that can be directly hit by the ESD, a ground line is placed near each signal line. |
| 124 | PCB layout and layout | Circuits that are susceptible to ESD are placed in the middle of the PCB to reduce the likelihood of being touched. |
| 125 | PCB layout and layout | When the length of the signal line is greater than 300mm (12 inches), be sure to lay a ground wire in parallel. |
| 126 | PCB layout and layout | Connection guidelines for mounting holes: can be connected to or isolated from the circuit. 1 When the metal bracket must be used with a metal shield or chassis, a 0Ω resistor is used for the connection. 2. Determine the mounting hole size to achieve reliable mounting of the metal or plastic bracket. Large pads should be used on the top and bottom of the mounting holes. Solder resists should not be used on the bottom pads, and the underlying pads are not soldered by wave soldering. |
| 127 | PCB layout and layout | Protected signal lines and unprotected signal lines are prohibited from being arranged in parallel. |
| 128 | PCB layout and layout | Wiring guidelines for reset, interrupt, and control signal lines: 1 with high frequency filtering; 2 away from input and output circuits; 3 away from board edges. |
| 129 | PCB layout and layout | The boards inside the chassis are not installed in the open position or in the internal seams. |
| 130 | PCB layout and layout | The most sensitive circuit board is placed in the middle, where it is not easily accessible by humans; the static-sensitive components are placed in the middle of the board, which is not easily accessible by humans. |
| 131 | PCB layout and layout | Binding criteria between two metal blocks: 1 solid bonding tape is better than woven bonding tape; 2 bonding is not wet without water; 3 using multiple conductors to ground the ground plane of all boards in the chassis Or the ground grids are connected together; 4 ensure that the width of the bonding points and washers is greater than 5 mm. |
| 132 | Circuit design | Signal Filter Leg Coupling: For each analog amplifier power supply, a decoupling capacitor must be added between the amplifiers closest to the circuit connection. For digital integrated circuits, add decoupling capacitors in groups. A capacitor bypass is installed on the brush of the motor and the generator, and an RC filter is connected in series on each winding branch, and low-pass filtering is added at the power inlet to suppress interference. Install the filter as close as possible to the device being filtered, using short, shielded leads as the coupling medium. All filters must be shielded and the input and output leads should be isolated. |
| 133 | Circuit design | Each function board clarifies the requirements of the voltage fluctuation range, ripple, noise, load adjustment rate, etc. of the power supply. The secondary power supply must meet the above requirements when it reaches the function board. |
| 134 | Circuit design | A circuit with radiation source characteristics is placed within the metal shield to minimize transient interference. |
| 135 | Circuit design | Add a protection device at the cable entrance |
| 136 | Circuit design | Each IC's power supply pin should be connected with a bypass capacitor (typically 104) and a smoothing capacitor (10uF~100uF) to ground. The power supply pins of each corner of the large-area IC should also be supplied with bypass capacitors and smoothing capacitors. |
| 137 | Circuit design | Impedance mismatch criteria for filter selection: For low impedance noise sources, the filter needs to be high impedance (large series inductance); for high impedance noise sources, the filter needs to be low impedance (large parallel capacitance) |
| 138 | Circuit design | Capacitor housing, auxiliary lead-out terminals must be completely isolated from the positive and negative terminals and the board |
| 139 | Circuit design | The filter connector must be well grounded and the metal shell filter grounded. |
| 140 | Circuit design | All pins of the filter connector are filtered |
| 141 | Circuit design | The electromagnetic compatibility design of digital circuits is to consider the frequency bandwidth determined by the rising and falling edges of the digital pulse rather than the repetition frequency of the digital pulse. The printed circuit board design bandwidth of a square digital signal is set to 1/Ï€tr, usually taking into account the bandwidth of this bandwidth. |
| 142 | Circuit design | Using R-S flip-flops as a buffer between the device control buttons and the device electronics |
| 143 | Circuit design | Reducing the input impedance of sensitive lines effectively reduces the likelihood of introducing interference. |
| 144 | Circuit design | LC Filter An LC filter is required between the low output impedance power supply and the high impedance digital circuit to ensure impedance matching of the loop. |
| 145 | Circuit design | Voltage calibration circuit: At the input and output terminals, a decoupling capacitor (such as 0.1μF) is added, and the bypass capacitor selection value follows the standard of 10μF/A. |
| 146 | Circuit design | Signal Termination: Impedance matching between the source and destination of the high frequency circuit is very important, and incorrect matching will result in signal feedback and damped oscillations. Excessive RF energy can cause EMI problems. At this point, you need to consider signal termination. |
| There are several types of signal terminations: series/source termination, parallel termination, | ||
| RC termination, Thevenin termination, diode termination. | ||
| 147 | Circuit design | MCU circuit: |
| I/O pin: The vacant I/O pin is connected to a high impedance to reduce the supply current. And avoid floating. | ||
| IRQ pin: Measures to prevent electrostatic discharge on the IRQ pin. For example, using bidirectional diodes, Transorbs or metal oxide varistor. | ||
| Reset pin: The reset pin has a time delay. In order to avoid the initial MCU is reset. | ||
| Oscillator: The lower the clock oscillation frequency used by the MCU, the better, if the requirements are met. | ||
| Let the clock circuit, calibration circuit and decoupling circuit be placed close to the MCU | ||
| 148 | Circuit design | A small-scale integrated circuit with less than 10 outputs, with a working frequency of ≤ 50 MHz, at least one 0.1 uf filter capacitor. When the operating frequency is ≥50MHZ, each power supply pin is connected with a 0.1uf filter capacitor; |
| 149 | Circuit design | For medium to large scale integrated circuits, each power supply pin is mated with a 0.1uf filter capacitor. For circuits with large power supply redundancy, the number of matching capacitors can be calculated according to the number of output pins, and a 0.1uf filter capacitor is connected to every 5 outputs. |
| 150 | Circuit design | For a region without active devices, connect at least one 0.1uf filter capacitor per 6cm2 |
| 151 | Circuit design | For UHF circuits, each power supply pin is mated with a 1000pf filter capacitor. For circuits with large power supply redundancy, the number of matching capacitors can also be calculated according to the number of output pins. Each 5 outputs is connected with a 1000pf filter capacitor. |
| 152 | Circuit design | The high frequency capacitor should be as close as possible to the power supply pin of the IC circuit. |
| 153 | Circuit design | At least one 0.1uf filter capacitor is connected to every 5 high frequency filter capacitors; |
| 154 | Circuit design | Each 5 10uf is equipped with at least two 47uf low frequency filter capacitors; |
| 155 | Circuit design | At least one 220uf or 470uf low frequency filter capacitor is connected every 100cm2; |
| 156 | Circuit design | At least 2 220uf or 470uf capacitors should be placed around the power outlet of each module. If space permits, the number of capacitors should be appropriately increased. |
| 157 | Circuit design | Pulse and transformer isolation criteria: The pulse network and the transformer must be isolated. The transformer can only be connected to the decoupling pulse network with the shortest connection line. |
| 158 | Circuit design | In the process of opening and closing the switch and the closet, in order to prevent arc interference, a simple RC network, an inductive network can be connected, and a high resistance, a rectifier or a load resistor is added to these circuits, and if not, Shield the input and output leads. In addition, a feedthrough capacitor can be connected to these circuits. |
| 159 | Circuit design | The decoupling and filter capacitors must be analyzed according to the high frequency equivalent circuit diagram. |
| 160 | Circuit design | Appropriate filter circuits should be used for the introduction of power supply for each function board. The differential mode noise and common mode noise should be filtered out at the same time. The noise discharge ground should be separated from the work ground, especially the signal ground. Consider using the protection ground; Decoupling capacitors should be placed at the input of the power supply to improve anti-interference ability |
| 161 | Circuit design | Defining the maximum operating frequency of each board and taking necessary shielding measures for devices or components with an operating frequency above 160MHz (or 200 MHz) to reduce the level of radiated interference and improve the ability to resist radiation interference |
| 162 | Circuit design | If possible, add RC decoupling at the entrance of the control line (on the printed board) to eliminate possible interference factors in the transmission. |
| 163 | Circuit design | Use RS trigger to make buffer between button and electronic circuit |
| 164 | Circuit design | Use a fast recovery diode in the secondary rectification loop or a polyester film capacitor in parallel with the diode |
| 165 | Circuit design | “Trimming†the transistor switching waveform |
| 166 | Circuit design | Reduce the input impedance of sensitive lines |
| 167 | Circuit design | If it is possible to use a balanced line as input in the sensitive circuit, use the common mode rejection capability inherent in the balanced line to overcome the interference of the interference source to the sensitive line. |
| 168 | Circuit design | The way to ground the load directly is not appropriate |
| 169 | Circuit design | Note that bypass decoupling capacitors (typically 104) are added between the power supply and ground at the near end of the IC. |
| 170 | Circuit design | If possible, the sensitive circuit uses a balanced line for input and the balanced line is not grounded. |
| 171 | Circuit design | The relay coil adds a freewheeling diode to eliminate back EMF interference when the coil is disconnected. Only adding a freewheeling diode will delay the turn-off time of the relay. After the Zener diode is added, the relay can move more times per unit time. |
| 172 | Circuit design | Spark suppression circuit is connected at both ends of the relay contact (generally RC series circuit, the resistance is generally selected from a few K to tens of K, and the c 4 layer PCB Board Storm Circuit Technology Ltd , https://www.stormpcb.com |