To accelerate certain computational tasks, we must first consider several key factors: which application needs to be accelerated, what the bottleneck of that application is, and then refer to existing work to choose an appropriate solution for that bottleneck. Jumping into the technical details of FPGAs too early can lead to unnecessary complexity. Nowadays, software-defined networks, flash storage, and other technologies are becoming mainstream trends.
**WHEN? Current Status of Heterogeneous Computing in Deep Learning**
With the rapid growth of internet users and the exponential increase in data volume, the demand for computing power in data centers is also rising sharply. At the same time, computationally intensive fields such as artificial intelligence, high-performance data analysis, and financial modeling have outpaced the capabilities of traditional CPU processors.
Heterogeneous computing is now seen as a critical technology to bridge this gap. The most popular platforms in the industry today include "CPU + GPU" and "CPU + FPGA," both of which offer higher efficiency and lower latency compared to traditional CPU-based parallel computing. With such a huge market opportunity, many tech companies have invested heavily in research and development, and standards for heterogeneous programming are gradually maturing. Major cloud service providers are actively integrating these technologies into their infrastructures.
**WHY? General CNN Acceleration Using FPGA**
It’s clear from industry trends that big companies like Microsoft have deployed large-scale FPGAs for AI inference acceleration. What makes FPGAs stand out compared to other devices?
**Flexibility: Natural Adaptation to Rapidly Evolving Machine Learning Algorithms**
FPGAs support a wide range of models including DNNs, CNNs, LSTMs, MLPs, reinforcement learning, and decision trees. They allow for arbitrary precision and dynamic support, enabling model compression, sparse networks, and faster, more efficient neural networks.
**Performance: Enabling Real-Time AI Services**
FPGAs offer significantly lower latency for predictions compared to GPUs or CPUs. They also deliver superior performance per watt, making them ideal for real-time applications.
**Scalability**
High-speed inter-board I/O and Intel CPU-FPGA architectures further enhance scalability. However, FPGAs do have some limitations. Development involves HDL (Hardware Description Language), leading to long development cycles and high entry barriers. For example, custom-developing acceleration for classic models like AlexNet or GoogLeNet can take several months. Balancing algorithm iteration with hardware acceleration between business teams and FPGA developers can be challenging.
To address these challenges, we designed a universal CNN accelerator. It supports fast model switching through a compiler-driven approach, reducing development time from months to just one or two weeks. This allows the development cycle to keep up with the rapid evolution of deep learning algorithms.
**HOW? Generic CNN FPGA Architecture**
The overall architecture of our generic CNN accelerator based on FPGA is as follows: Models trained using frameworks like Caffe, TensorFlow, or MXNet generate optimized instructions via a compiler. Image data and model weights are preprocessed and compressed before being sent to the FPGA via PCIe. The FPGA executes these instructions efficiently, with each functional module handling specific calculations independently. Data dependencies and layer relationships are managed within the instruction set, separating the accelerator from the deep learning model itself.
In simple terms, the compiler's role is to analyze and optimize the model structure, generating an efficient instruction set for the FPGA. The optimization goal is to maximize MAC (Multiply-Accumulate) DSP efficiency while minimizing memory access.
Let’s take GoogLeNet V1 as an example. Its Inception modules combine 1x1, 3x3, 5x5 convolutions, and 3x3 pooling, increasing network bandwidth and adaptability. By analyzing data dependencies and parallelism, we can optimize the pipeline and memory access, ensuring maximum utilization of computational resources.
For model optimization, we focus on finding structural improvements and supporting fixed-point operations for dynamic precision. In GoogLeNet V1, overlapping feature maps reduces memory usage by a third. We also support int16 fixed-point operations with dynamic adjustment, allowing direct deployment of floating-point models without retraining.
Our memory architecture minimizes DDR access by using ping-pong buffers, internal copying, and cross-copying. This design enables most models to run entirely on the FPGA chip, reducing external memory operations.
The core of the accelerator is its computing unit. Based on the Xilinx KU115 chip, it features 4096 MAC DSP cores operating at 500MHz, offering a theoretical peak of 4 Tflops. The design emphasizes data reuse to reduce bandwidth and improve efficiency.
**Application Scenarios and Performance Comparison**
While GPUs are commonly used for training, FPGAs excel in online inference due to their low latency, low cost, and energy efficiency. They are ideal for real-time AI services like advertising recommendation, voice recognition, and video monitoring, as well as low-power scenarios such as smart speakers and autonomous vehicles.
In terms of performance, a single KU115-based accelerator delivers 16 times the CPU performance for GoogLeNet V1, reducing detection delay from 250ms to 4ms and cutting TCO by 90%. Compared to the NVIDIA P4 GPU, it offers similar performance but with orders of magnitude lower latency.
**Development Cycle and Ease of Use**
The flexible CNN FPGA architecture supports fast iterations of deep learning models, including classics like GoogLeNet, VGG, ResNet, and newer variants. Compiling instructions for standard models takes just one day, while custom models require 1–2 weeks.
The FPGA CNN accelerator provides an easy-to-use SDK, allowing businesses to call simple APIs for acceleration with minimal changes to their logic. Model updates can be done in seconds by initializing the new instruction set.
**Conclusion**
Our FPGA-based CNN accelerator significantly shortens development cycles and supports rapid algorithm iteration. It matches GPU performance but offers better latency, making it ideal for real-time AI services. As we continue developing versatile RNN/DNN platforms, we’re building robust AI capabilities for businesses.
In 2017, we launched the first public FPGA server on Tencent Cloud, and we plan to expand these AI acceleration capabilities to the broader cloud. The future of AI heterogeneous computing is exciting, and our FPGA team is committed to delivering the best solutions for both company and cloud-based businesses.
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