To accelerate certain computational tasks, we must first address several key considerations: which application to accelerate, what the performance bottleneck is, and then refer to previous work to select the most suitable solution for that bottleneck. Jumping into the technical details of FPGAs too early can lead to unnecessary complexity. With trends like software-defined networks, flash storage, and other emerging technologies, it's clear that flexibility and adaptability are becoming more important than ever.
**WHEN? The Current State of Deep Learning Heterogeneous Computing**
With the rapid growth of internet users and the exponential increase in data volume, the demand for computing power in data centers has surged. At the same time, computationally intensive fields such as artificial intelligence, high-performance data analysis, and financial modeling have pushed traditional CPU processors beyond their limits.
Heterogeneous computing is now seen as a crucial technology to bridge this gap. Among the most popular platforms today are "CPU+GPU" and "CPU+FPGA," both of which offer higher efficiency and lower latency compared to traditional CPU-based parallel computing. With a huge market opportunity, many tech companies have invested heavily in research and development, and the standards for heterogeneous programming are gradually maturing. Major cloud providers are also actively integrating these solutions into their infrastructures.
**WHY? General CNN Acceleration with FPGA**
Major companies like Microsoft have already deployed large-scale FPGAs for AI inference acceleration. What makes FPGAs stand out?
**Flexibility:** FPGAs offer natural adaptability to rapidly evolving machine learning algorithms, including DNNs, CNNs, LSTMs, MLPs, reinforcement learning, and decision trees. They support arbitrary precision and dynamic adjustments, enabling model compression, sparse networks, and faster, more efficient models.
**Performance:** FPGAs deliver low-latency predictions and superior single-watt performance compared to GPUs and CPUs.
**Scalability:** High-speed interconnects between boards and Intel’s CPU-FPGA architecture allow for seamless integration.
However, FPGAs also have limitations. Development using HDL languages is time-consuming and has a steep learning curve. Customizing an accelerator for models like AlexNet or GoogLeNet can take months, requiring close collaboration between the algorithm team and the hardware team, which can be challenging.
To address these issues, we designed a universal CNN accelerator. By leveraging a compiler-driven approach, it supports quick model switching and reduces development time from months to just one or two weeks. This allows for faster iteration with new deep learning algorithms.
**HOW? A Generic CNN FPGA Architecture**
The general framework of our CNN accelerator based on FPGA involves generating optimized instructions from models trained in frameworks like Caffe, TensorFlow, or MXNet. These instructions are then executed by the FPGA, which processes image and weight data efficiently through PCIe. Each functional module operates independently, controlled by the instruction set, allowing for modular computation and separation from the deep learning model itself.
In simple terms, the compiler optimizes the model structure to maximize MAC (Multiply-Accumulate) efficiency and minimize memory access. For example, in GoogLeNet v1, the Inception module combines multiple convolution layers and pooling operations. Through data dependency analysis and parallelism optimization, we can overlap calculations and reduce memory usage significantly.
**Model Optimization**
We focus on finding structural optimizations and supporting dynamic precision adjustment. In GoogLeNet v1, we align outputs from different branches to reduce memory demand. We also use a fixed-point int16 scheme with dynamic precision adjustment to maintain accuracy without retraining the model.
**Memory Architecture Design**
Minimizing DDR memory access is critical for performance. Our design includes ping-pong buffers, internal copy operations, and cross-copy mechanisms to optimize pipeline and parallelism. For larger models, we implement slice fragmentation and feature map partitioning to balance memory access and computation.
**Computing Unit Design**
The core of the accelerator is its PE (Processing Element) units. Based on the Xilinx KU115 chip, each PE contains 4 sets of 32x16=512 MAC cores operating at 500MHz, offering a theoretical peak of 4 Tflops. The design emphasizes data reuse to reduce bandwidth and improve efficiency.
**Application Scenarios and Performance Comparison**
FPGAs excel in real-time and low-power scenarios, such as advertising, voice recognition, video monitoring, smart traffic, and IoT devices. Compared to GPUs, they offer better latency and comparable performance. For example, a single KU115-based accelerator can achieve 16 times the CPU performance, reducing detection delay from 250ms to 4ms, and cutting TCO by 90%.
**Development Cycle and Ease of Use**
Our architecture supports fast iterations of deep learning models, including classic ones like GoogLeNet, VGG, ResNet, and newer variants. Compiling instructions for standard models takes just one day, while custom models can be developed within one to two weeks.
The FPGA CNN accelerator provides an easy-to-use SDK, allowing businesses to call simple APIs without modifying their existing logic. Model changes can be implemented in seconds by updating the instruction set.
**Conclusion**
The FPGA-based universal CNN accelerator significantly reduces development cycles and supports rapid iteration of deep learning algorithms. It offers competitive performance to GPUs with lower latency, making it ideal for real-time AI services. As part of Tencent Cloud’s AI acceleration strategy, we continue to refine and expand these capabilities, aiming to provide the best solutions for both company and cloud applications.
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