A well-designed PCB layout enhances efficiency, reduces thermal stress, and minimizes the impact of noise between traces and components. These benefits stem from the designer's deep understanding of the current conduction path and signal flow within the circuit. When a prototype power board is first tested, ideally it works smoothly, runs quietly, and generates minimal heat. However, this ideal scenario is rare.
One common issue in switching power supplies is an unstable switching waveform. In some cases, jitter in the magnetic components can lead to audible noise. If the problem lies in the PCB layout, identifying the cause can be challenging. Therefore, implementing a proper PCB layout from the start of the design process is crucial for reliable performance.
A good layout optimizes power efficiency, slows thermal stress, and most importantly, minimizes noise and interference between traces and components. To achieve these goals, designers must have a clear understanding of the current path and signal flow within the switching power supply. This article provides key lessons on the correct PCB layout for non-isolated switching power supplies.
**Layout Planning**
For an embedded DC/DC power supply on a large board, placing the power supply output close to the load device ensures optimal voltage regulation, fast load transient response, and improved system efficiency. This minimizes interconnect impedance and voltage drop across PCB traces. Good airflow should also be ensured, and thermal stress should be limited. If forced air cooling is used, the power supply should be positioned near the fan.
Large passive components like inductors and electrolytic capacitors should not block airflow over low-profile semiconductor components such as power MOSFETs or PWM controllers. To prevent switching noise from interfering with analog signals, sensitive signal lines should be kept away from the power supply area. If this isn't possible, an internal ground plane should be placed between the power supply layer and the small signal layer for shielding.
The key to a successful layout is planning the placement of the power supply and allocating sufficient board space during the early stages of the design. Unfortunately, many designers overlook this advice, focusing instead on more "exciting" circuits on large system boards. Power management is often treated as an afterthought, leading to inefficient and unreliable power supply designs.
In multilayer boards, a good practice is to place a DC input/output voltage layer between the high-current power component layer and the sensitive small signal trace layer. This DC voltage layer acts as an AC ground, shielding small signal traces from high-noise power traces and components.
As a general rule, the ground plane or DC voltage layer in a multilayer PCB should remain unbroken. If separation is unavoidable, the number and length of traces on these layers should be minimized, and routing should follow the same direction as the large current to reduce noise effects.
The figures below show poor and good layer structures for six-layer and four-layer switching power supply PCBs. The poor structures sandwich the small signal layer between the high-current power layer and the ground plane, increasing capacitive coupling and noise. The good structures use a ground plane to shield the small signal layer and keep the power layer adjacent to the outer layer.
**Power Stage Layout**
The switching power supply circuit can be divided into two parts: the power stage, which handles large currents, and the small signal control circuit. Typically, the power stage components are placed first, followed by the small signal control circuit at specific locations on the board.
High current traces should be short and wide to minimize PCB inductance, resistance, and voltage drop—especially for traces carrying high di/dt pulse currents.
The figure shows the continuous and pulse current paths in a synchronous buck converter. The solid line represents the continuous current path, while the dashed line shows the pulse (switch) current path. This includes traces connected to the input decoupling capacitor, upper FET, lower FET, and optionally a Schottky diode.
Parasitic inductance in the pulse current path causes magnetic field radiation and voltage ringing on the PCB and MOSFETs. To minimize inductance, the pulse current loop (thermal circuit) should have the smallest possible area, with short and wide traces.
The high-frequency decoupling capacitor CHF should be a 0.1μF–10μF X5R or X7R ceramic capacitor with low ESL and ESR. Larger dielectrics like Y5V may lose capacitance under varying voltage and temperature conditions, making them unsuitable for CHF.
The layout example in Figure 3b shows how to minimize the thermal loop area in a buck converter. Power components should be placed on the same side of the board, with power traces on the same layer. When moving power lines to another layer, choose a trace in the continuous current path. Use multiple vias to connect layers in high current loops to reduce impedance.
Figure 4 illustrates the continuous and pulse current paths in a boost converter, with the high-frequency capacitor placed near the MOSFET and boost diode. The key is to minimize the loop formed by the switching transistor, rectifier diode, and output capacitor.
**High dv/dt Switch Area**
In Figures 2 and 4, the switch node has a high dv/dt rate, creating rich high-frequency noise and acting as a source of EMI. To reduce coupling between the switch junction and other sensitive traces, keep the copper area as small as possible. However, enough area is needed to conduct inductor currents and provide heat dissipation for the MOSFET. A grounded copper foil under the switch junction helps shield the area.
If there’s no heat sink, the copper area must provide sufficient heat dissipation. For DC voltage junctions, larger copper areas are recommended. Multiple vias help reduce thermal stress. A balance must be struck between minimizing noise and ensuring adequate heat dissipation.
**Control Circuit Layout**
Keep the control circuit away from high-noise switch areas. For a buck converter, place the control circuit near the VOUT+ terminal. For a boost converter, place it near the VIN+ terminal to allow the power trace to carry continuous current.
If space allows, maintain a distance of 0.5 to 1 inch between the control IC and power components. If space is tight, isolate the control circuit using ground traces. The control circuit should have a separate signal (analog) ground from the power ground. If the controller IC has SGND and PGND pins, route them separately. For ICs with integrated drivers, use SGND for the small signal portion.
Only one connection point should exist between the signal and power grounds. A clean return point in the power ground is ideal. Two grounding traces under the controller IC can provide this connection.
This pad should be soldered to the PCB to reduce electrical and thermal resistance. Place multiple vias in the ground pad area.
**Loop Area and Crosstalk**
Adjacent conductors can create capacitive coupling. High dv/dt on one conductor can couple noise to another through parasitic capacitance. To reduce noise from the power stage to the control circuit, keep high-noise traces away from sensitive signal traces. If possible, place them on different layers and use an internal ground plane as a shield.
When space allows, maintain a small distance between the control IC and power components. This helps reduce interference and heat buildup.
**Trace Width Selection**
Different signals require different trace widths based on controller pins, current levels, and noise sensitivity. Small signal networks typically use 10–15 mil traces. High current networks (gate drive, VCC, and PGND) should be wider, with width determined by current requirements.
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