Now, an innovative architecture is needed to manage hundreds of Gbps of system performance to achieve intelligent processing at full line rate and scale to Tb performance and 1 billion floating point operations per second. The necessary requirements for achieving the above requirements are not just to improve the performance of each transistor or system module, or to increase the number of system modules, but to fundamentally improve communication, clock, critical path and interconnection performance to meet the new generation of the industry. High-performance applications (shown below) for massive data streams and intelligent packet, DSP or image processing requirements.
Figure 1 Prerequisites for an ASIC-level programmable architecture
The UltraScaleTM architecture addresses these challenges by applying state-of-the-art ASIC technology to a fully programmable architecture. The architecture can scale from a 20nm planar FET structure to a 16nm fin FET transistor technology and even higher technology, while extending from a single chip to a 3D IC. The UltraScale architecture not only addresses the limitations of total system throughput expansion and latency, but also directly addresses the number one system performance bottleneck on advanced process nodes, namely interconnect issues.
Figure 2: Prerequisites for an ASIC-level programmable architecture
The UltraScaleTM architecture delivers unparalleled levels of high integration, high capacity, and ASIC-level system performance to meet the most demanding applications. The UltraScale architecture is fine-tuned to provide large-scale cabling capabilities and is optimized for collaboration with Vivado® design tools, so the architecture's utilization is at an unprecedentedly high level (over 90%) without compromising performance.
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